Semiconductor Devices in Harsh Conditions

This book introduces the reader to a number of challenges for the operation of electronic devices in various harsh environmental conditions. While some chapters focus on measuring and understanding the effects of these environments on electronic components, many also propose design solutions, whether in choice of material, innovative structures, or strategies for amelioration and repair. Many applications need electronics designed to operate in harsh environments. Readers will find, in this collection of topics, tools and ideas useful in their own pursuits and of interest to their intellectual curiosity

COTS – Harsh Condition Effects Considerations from Technology to User Level

Radiation hardened devices are mostly extremely expensive. The continuously downscaling of microelectronic structures and the unavoidable presence of particle radiation on ground and in space leads to unwanted failures in electronic devices. Furthermore it is expected that in the next few years around 8000 new satellites will be launched around the world. Due to the enormous increasing need for Rad-Hard devices, there will be more focus on Commercial Of The Shelf (COTS) devices, which costs are lower. Also nowadays microelectronics for automotive systems are tested to withstand radiation especially SEU-single event upsets. It is clear that SEU cannot be ignored anymore especially in the application of unmanned autonomous vehicles and systems. Reliability testing is expensive and extremely time consuming. The use of COTS-Commercials of the shelf is the ultimate goal to reach. In this paper, an overview of radiation effects on different CMOS technologies used in COTS devices is given. These effects can be considered while selecting different functional equivalent COTS devices implemented with different technologies. Moreover, an overview of software techniques used in programmable commercial devices to reduce the radiation effects is also described

“New automotive” — Considerations for reliability, robustness and resilience for CMOS interconnects

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